The present invention is related to U.S. patent application Ser. No. 09/416,899, entitled "CMOS VOLTAGE REFERENCE WITH A NULLING AMPLIFIER", filed Oct. 13, 1999; U.S. patent application Ser. No. 09/416,896, entitled "SLOPE AND LEVEL TRIM DAC FOR VOLTAGE REFERENCE", filed Oct. 13, 1999; and U.S. patent application Ser. No. 09/416,897, entitled "CMOS VOLTAGE REFERENCE WITH POST ASSEMBLY CURVATURE TRIM", filed Oct. 13, 1999; all applications are commonly assigned to the assignee of the present invention, and the disclosures of which are herein incorporated by reference.
1. Field of the Invention
The present invention relates generally to the field of low dropout references, and more particularly to a low dropout reference amplifier circuit that is stable under various load conditions.
2. Description of the Related Art
FIG. 1(A) is a block diagram of a conventional low dropout (LDO) voltage reference. The stability of this type of LDO reference is highly dependent on the load attached to Vout. This load dependence is due to the high impedance of the drain terminal of the p-channel output pass FET M11 that results in a low frequency pole, which introduces a phase shift in the feedback loop. In addition to the stability problems, the line regulation of the conventional reference is poor due in part to the fact that the drain voltages of the cascode p-channel FETs M5, M6 are not constant under all operating conditions. The drain voltage variance results in a differential error current due to the Early effect and/or unbalanced leakage currents from the drain to well junctions. The differential error current will produce an input referred offset error that is power supply dependent. FIG. 1(B) is a schematic of a typical implementation of the conventional LDO circuit of FIG. 1(A).
A low dropout voltage regulator is disclosed in U.S. Pat. No. 5,672,959, entitled "LOW DROP-OUT VOLTAGE REGULATOR HAVING HIGH RIPPLE REJECTION AND LOW POWER CONSUMPTION." The disclosed circuit relies on an external load capacitance to stabilize one of the two feedback loops. This has a similar disadvantage in that the circuit performance is dependent upon the load.
In view of the foregoing, it would be desirable to have a low dropout voltage reference that is stable under various loading conditions and has improved power supply rejection.